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1

Analysis of charge-pump phase-locked loops

Hanumolu, P.K., Brownlee, M., Mayaram, K., Un-Ku Moon

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2004

Language:

english

File:

PDF, 925 KB

english, 2004

2

[IEEE 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - Pune, India (2018.1.6-2018.1.10)] 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers

Khan, Qadeer A., Kim, Seong-Joong, Hanumolu, Pavan Kumar

Year:

2018

Language:

english

File:

PDF, 559 KB

english, 2018

3

A semi-synchronous SAR ADC

Tong, Tao, Hanumolu, Pavan K., Temes, Gabor C.

Journal:

Analog Integrated Circuits and Signal Processing

Year:

2012

Language:

english

File:

PDF, 266 KB

english, 2012

4

Analog Filter Design Using Ring Oscillator Integrators

Drost, Brian, Talegaonkar, Mrunmay, Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2012

Language:

english

File:

PDF, 1.58 MB

english, 2012

5

Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops

Arakali, Abhijith, Gondi, Srikanth, Hanumolu, Pavan Kumar

Journal:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Year:

2010

Language:

english

File:

PDF, 1.66 MB

english, 2010

6

Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay

Wang, Yan, Hanumolu, Pavan Kumar, Temes, Gábor C.

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2011

Language:

english

File:

PDF, 1.57 MB

english, 2011

7

[IEEE 2012 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2012.06.13-2012.06.15)] 2012 Symposium on VLSI Circuits (VLSIC) - A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control

Khan, Qadeer, Elshazly, Amr, Rao, Sachin, Inti, Rajesh, Hanumolu, Pavan Kumar

Year:

2012

Language:

english

File:

PDF, 604 KB

english, 2012

8

[IEEE 2006 IEEE International Symposium on Circuits and Systems - Island of Kos, Greece (21-24 May 2006)] 2006 IEEE International Symposium on Circuits and Systems - Constant Transconductance Bias Circuit with an On-Chip Resistor

Talebbeydokhti, N., Hanumolu, P.K., Kurahashi, P., Un-Ku Moon,

Year:

2006

Language:

english

File:

PDF, 3.36 MB

english, 2006

9

[IEEE 2020 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2020.2.16-2020.2.20)] 2020 IEEE International Solid- State Circuits Conference - (ISSCC) - 3.2 A 0.0088mm 2 Resistor-Based Temperature Sensor Achieving 92fJÂ·K 2 FoM in 65nm CMOS

Khashaba, Amr, Zhu, Junheng, Elmallah, Ahmed, Ahmed, Mostafa, Hanumolu, Pavan Kumar

Year:

2020

File:

PDF, 1.21 MB

2020

10

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Elshazly, A., Inti, R., Young, B., Hanumolu, P. K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2013

Language:

english

File:

PDF, 2.96 MB

english, 2013

11

[IEEE 2018 IEEE Custom Integrated Circuits Conference (CICC) - San Diego, CA (2018.4.8-2018.4.11)] 2018 IEEE Custom Integrated Circuits Conference (CICC) - A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

Elmallah, Ahmed, Ahmed, Mostafa Gamal, Elkholy, Ahmed, Choi, Woo-Seok, Hanumolu, Pavan Kumar

Year:

2018

Language:

english

File:

PDF, 680 KB

english, 2018

12

Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers

Megawer, Karim M., Elkholy, Ahmed, Ahmed, Mostafa Gamal, Elmallah, Ahmed, Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2018

Language:

english

File:

PDF, 4.35 MB

english, 2018

13

Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS

Assem, Pourya, Liu, Wen-Chuen, Lei, Yutian, Hanumolu, Pavan Kumar, Pilawa-Podgurski, Robert C. N.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2020

File:

PDF, 6.00 MB

2020

14

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Elkholy, Ahmed, Saxena, Saurabh, Nandwana, Romesh Kumar, Elshazly, Amr, Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2016

Language:

english

File:

PDF, 3.13 MB

english, 2016

15

[IEEE 2018 IEEE Custom Integrated Circuits Conference (CICC) - San Diego, CA (2018.4.8-2018.4.11)] 2018 IEEE Custom Integrated Circuits Conference (CICC) - A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR

Kim, Dongwook, Choi, Woo-Seok, Elkholy, Ahmed, Kenney, Jack, Hanumolu, Pavan Kumar

Year:

2018

Language:

english

File:

PDF, 346 KB

english, 2018

16

[IEEE 2011 IEEE Custom Integrated Circuits Conference - CICC 2011 - San Jose, CA, USA (2011.09.19-2011.09.21)] 2011 IEEE Custom Integrated Circuits Conference (CICC) - Digital clock and data recovery circuit design: Challenges and tradeoffs

Talegaonkar, Mrunmay, Inti, Rajesh, Hanumolu, Pavan Kumar

Year:

2011

Language:

english

File:

PDF, 288 KB

english, 2011

17

[IEEE 2015 IEEE Custom Integrated Circuits Conference - CICC 2015 - San Jose, CA, USA (2015.9.28-2015.9.30)] 2015 IEEE Custom Integrated Circuits Conference (CICC) - Low dropout regulators

Hanumolu, Pavan Kumar

Year:

2015

File:

PDF, 2.92 MB

2015

18

[IEEE 2017 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2017.2.5-2017.2.9)] 2017 IEEE International Solid-State Circuits Conference (ISSCC) - 8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Coombs, Daniel, Elkholy, Ahmed, Nandwana, Romesh Kumar, Elmallah, Ahmed, Hanumolu, Pavan Kumar

Year:

2017

Language:

english

File:

PDF, 12.09 MB

english, 2017

19

EQUALIZERS FOR HIGH-SPEED SERIAL LINKS

HANUMOLU, PAVAN KUMAR, WEI, GU-YEON, MOON, UN-KU

Journal:

International Journal of High Speed Electronics and Systems

Year:

2005

Language:

english

File:

PDF, 1.37 MB

english, 2005

20

[IEEE 2011 IEEE Custom Integrated Circuits Conference - CICC 2011 - San Jose, CA, USA (2011.09.19-2011.09.21)] 2011 IEEE Custom Integrated Circuits Conference (CICC) - A high-PSR LDO using a feedforward supply-noise cancellation technique

Yang, Bangda, Drost, Brian, Rao, Sachin, Hanumolu, Pavan Kumar

Year:

2011

Language:

english

File:

PDF, 262 KB

english, 2011

21

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Kim, Dongwook, Ahmed, Mostafa G., Choi, Woo-Seok, Elkholy, Ahmed, Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2020

Language:

english

File:

PDF, 778 KB

english, 2020

22

[IEEE ESSCIRC 2011 - 37th European Solid State Circuits Conference - Helsinki, Finland (2011.09.12-2011.09.16)] 2011 Proceedings of the ESSCIRC (ESSCIRC) - A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control

Khan, Qadeer, Rao, Sachin, Swank, Damian, Rao, Arun, McIntyre, William, Bang, Sarvesh, Hanumolu, Pavan K

Year:

2011

Language:

english

File:

PDF, 1.38 MB

english, 2011

23

[IEEE 2016 IEEE International Solid-State Circuits Conference (ISSCC) - San Francisco, CA, USA (2016.1.31-2016.2.4)] 2016 IEEE International Solid-State Circuits Conference (ISSCC) - 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Shu, Guanghua, Choi, Woo-Seok, Saxena, Saurabh, Kim, Seong-Joong, Talegaonkar, Mrunmay, Nandwana, Romesh, Elkholy, Ahmed, Wei, Da, Nandi, Timir, Hanumolu, Pavan Kumar

Year:

2016

Language:

english

File:

PDF, 32.38 MB

english, 2016

24

New Associate Editors

Kumar Hanumolu, Pavan

Journal:

IEEE Journal of Solid-State Circuits

Year:

2020

File:

PDF, 2.62 MB

2020

25

[IEEE 2017 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2017.2.5-2017.2.9)] 2017 IEEE International Solid-State Circuits Conference (ISSCC) - 29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS

Nandwana, Romesh Kumar, Saxena, Saurabh, Elkholy, Ahmed, Talegaonkar, Mrunmay, Zhu, Junheng, Choi, Woo-Seok, Elmallah, Ahmed, Hanumolu, Pavan Kumar

Year:

2017

Language:

english

File:

PDF, 17.66 MB

english, 2017

26

A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator

Kim, Seong Joong, Nandwana, Romesh Kumar, Khan, Qadeer, Pilawa-Podgurski, Robert C. N., Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2015

Language:

english

File:

PDF, 2.80 MB

english, 2015

27

A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity

Anand, Tejasvi, Makinwa, Kofi A. A., Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2016

Language:

english

File:

PDF, 3.49 MB

english, 2016

28

[IEEE 2017 IEEE Custom Integrated Circuits Conference (CICC) - Austin, TX, USA (2017.4.30-2017.5.3)] 2017 IEEE Custom Integrated Circuits Conference (CICC) - Time-based ΑΣADCs

Hanumolu, Pavan Kumar

Year:

2017

Language:

english

File:

PDF, 2.07 MB

english, 2017

29

[IEEE 2019 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2019.2.17-2019.2.21)] 2019 IEEE International Solid- State Circuits Conference - (ISSCC) - 18.5 A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS

Megawer, Karim M., Pal, Nilanjan, Elkholy, Ahmed, Ahmed, Mostafa G., Khashaba, Amr, Griffith, Danielle, Hanumolu, Pavan Kumar

Year:

2019

File:

PDF, 6 KB

2019

30

[IEEE 2009 IEEE Custom Integrated Circuits Conference (CICC) - San Jose, CA, USA (2009.09.13-2009.09.16)] 2009 IEEE Custom Integrated Circuits Conference - Over-sampled data converters

Hanumolu, Pavan Kumar, Piovaccari, Alessandro

Year:

2009

Language:

english

File:

PDF, 126 KB

english, 2009

31

[IEEE IEEE Custom Integrated Circuits Conference 2006 - San Jose, CA, USA (2006.09.10-2006.09.13)] IEEE Custom Integrated Circuits Conference 2006 - A 1.6Gbps Digital Clock and Data Recovery Circuit

Hanumolu, Pavan, Kim, Min, Wei, Gu-yeon, Moon, Un-ku

Year:

2006

Language:

english

File:

PDF, 277 KB

english, 2006

32

[IEEE 2014 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2014.6.10-2014.6.13)] 2014 Symposium on VLSI Circuits Digest of Technical Papers - A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW

Khan, Qadeer, Seong Joong Kim,, Talegaonkar, Mrunmay, Elshazly, Amr, Rao, Arun, Griesert, Nathanael, Winter, Greg, McIntyre, Willam, Hanumolu, Pavan Kumar

Year:

2014

Language:

english

File:

PDF, 657 KB

english, 2014

33

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - An FMDLL Based Dual-Loop Frequency Synthesizer for 5GHz WLAN Applications

Ting Wu,, Hanumolu, P.K., Un-Ku Moon,, Mayaram, K.

Year:

2005

Language:

english

File:

PDF, 228 KB

english, 2005

34

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Jitter in high-speed serial and parallel links

Hanumolu, P.K., Casper, B., Mooney, R., Gu-Yeon Wei,, Un-Ku Moon,

Year:

2004

Language:

english

File:

PDF, 304 KB

english, 2004

35

[IEEE 2016 IEEE International Solid-State Circuits Conference (ISSCC) - San Francisco, CA, USA (2016.1.31-2016.2.4)] 2016 IEEE International Solid-State Circuits Conference (ISSCC) - 19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS

Zhu, Junheng, Nandwana, Romesh Kumar, Shu, Guanghua, Elkholy, Ahmed, Kim, Seong-Joong, Hanumolu, Pavan Kumar

Year:

2016

Language:

english

File:

PDF, 24.78 MB

english, 2016

36

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

Choi, Woo-Seok, Anand, Tejasvi, Shu, Guanghua, Elshazly, Amr, Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2015

Language:

english

File:

PDF, 2.78 MB

english, 2015

37

[IEEE 2015 IEEE Custom Integrated Circuits Conference - CICC 2015 - San Jose, CA, USA (2015.9.28-2015.9.30)] 2015 IEEE Custom Integrated Circuits Conference (CICC) - A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter

Elkholy, Ahmed, Saxena, Saurabh, Nandwana, Romesh Kumar, Elshazly, Amr, Hanumolu, Pavan Kumar

Year:

2015

Language:

english

File:

PDF, 775 KB

english, 2015

38

[IEEE 2010 IEEE Custom Integrated Circuits Conference -CICC 2010 - San Jose, CA, USA (2010.09.19-2010.09.22)] IEEE Custom Integrated Circuits Conference 2010 - A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS

Yin, Wenjing, Inti, Rajesh, Hanumolu, Pavan Kumar

Year:

2010

Language:

english

File:

PDF, 628 KB

english, 2010

39

[IEEE 2010 IEEE Custom Integrated Circuits Conference -CICC 2010 - San Jose, CA, USA (2010.09.19-2010.09.22)] IEEE Custom Integrated Circuits Conference 2010 - A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer

Chae, J., Lee, S., Aniya, M., Takeuchi, S., Hamashita, K., Hanumolu, P. K., Temes, G. C.

Year:

2010

Language:

english

File:

PDF, 184 KB

english, 2010

40

A 5 GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS

Talegaonkar, Mrunmay, Anand, Tejasvi, Elkholy, Ahmed, Elshazly, Amr, Nandwana, Romesh Kumar, Saxena, Saurabh, Young, Brian, Choi, Woo-Seok, Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2017

Language:

english

File:

PDF, 5.74 MB

english, 2017

41

Frequency detector for fast frequency lock of digital PLLs

Kratyuk, V., Hanumolu, P.K., Moon, U.-K., Mayaram, K.

Journal:

Electronics Letters

Year:

2007

Language:

english

File:

PDF, 138 KB

english, 2007

42

A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques

Khashaba, Amr, Elkholy, Ahmed, Megawer, Karim M., Ahmed, Mostafa Gamal, Hanumolu, Pavan Kumar

Journal:

IEEE Journal of Solid-State Circuits

Year:

2019

File:

PDF, 4.36 MB

2019

43

[IEEE 2020 IEEE Custom Integrated Circuits Conference (CICC) - Boston, MA, USA (2020.3.22-2020.3.25)] 2020 IEEE Custom Integrated Circuits Conference (CICC) - A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS

Pal, Nilanjan, Fish, Adam, McIntyre, William, Griesert, Nathanael, Winter, Greg, Eichhorn, Travis, Pilawa-Podgurski, Robert, Hanumolu, Pavan Kumar

Year:

2020

File:

PDF, 2.49 MB

2020

44

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

Min Gyu Kim, Gil-Cho Ahn, Hanumolu, P.K., Sang-Hyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Temes, G.C., Un-Ku Moon

Journal:

IEEE Journal of Solid-State Circuits

Year:

2008

Language:

english

File:

PDF, 2.24 MB

english, 2008

45

[IEEE 2009 IEEE Custom Integrated Circuits Conference (CICC) - San Jose, CA, USA (2009.09.13-2009.09.16)] 2009 IEEE Custom Integrated Circuits Conference - An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing

Kwon, Sunwoo, Hanumolu, Pavan Kumar, Kim, Sang-Ho, Lee, Sung-No, You, Seung-Bin, Park, Ho-Jin, Kim, Jae-Whui, Moon, Un-Ku

Year:

2009

Language:

english

File:

PDF, 1.01 MB

english, 2009

46

[IEEE 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012 - Seoul, Korea (South) (2012.05.20-2012.05.23)] 2012 IEEE International Symposium on Circuits and Systems - Calibration technique for SAR analog-to-digital converters

Tong, Tao, Yu, Wenhuan, Hanumolu, Pavan K., Temes, Gabor C.

Year:

2012

Language:

english

File:

PDF, 541 KB

english, 2012

47

[IEEE 2010 IEEE Custom Integrated Circuits Conference -CICC 2010 - San Jose, CA, USA (2010.09.19-2010.09.22)] IEEE Custom Integrated Circuits Conference 2010 - A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth

Young, Brian, Kwon, Sunwoo, Elshazly, Amr, Hanumolu, Pavan Kumar

Year:

2010

Language:

english

File:

PDF, 430 KB

english, 2010

48

[IEEE 2008 IEEE Custom Integrated Circuits Conference - CICC 2008 - San Jose, CA, USA (2008.09.21-2008.09.24)] 2008 IEEE Custom Integrated Circuits Conference - A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of −28dB

Arakali, Abhijith, Gondi, Srikanth, Hanumolu, Pavan Kumar

Year:

2008

Language:

english

File:

PDF, 414 KB

english, 2008

49

[IEEE IEEE Custom Integrated Circuits Conference 2006 - San Jose, CA, USA (2006.09.10-2006.09.13)] IEEE Custom Integrated Circuits Conference 2006 - A 0.6V Highly Linear Switched-R-MOSFET-C Filter

Kurahashi, Peter, Hanumolu, Pavan, Temes, Gabor, Moon, Un-ku

Year:

2006

Language:

english

File:

PDF, 201 KB

english, 2006

50

[IEEE 2017 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2017.2.5-2017.2.9)] 2017 IEEE International Solid-State Circuits Conference (ISSCC) - EE4: Semiconductor economics: How business decisions are engineered

Fujimori, Ichiro, Hanumolu, Pavan, Fujimori, Ichiro

Year:

2017

Language:

english

File:

PDF, 980 KB

english, 2017

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